1. Field of the Invention
The present invention relates to a variable resistance circuit varying the resistance value thereof by turning on/off a plurality of switches connected in parallel with a plurality of serially connected resistors respectively, an operational amplification circuit employing this variable resistance circuit, a semiconductor integrated circuit employing this operational amplification circuit, a time constant switching circuit, and a waveform shaping circuit, having a small number of time constant errors, using this time constant switching circuit.
2. Description of the Prior Art
In recent years, optical disk drives such as a CD (compact disk) drive, a CD-ROM (compact disk read only memory) drive and the like come into wide use, followed by development of various semiconductor integrated circuits applied to these optical disk drives.
FIG. 14 is a block diagram showing the structure of a conventional semiconductor integrated circuit applied to a CD-ROM drive.
The circuit shown in FIG. 14, formed by a plurality of semiconductor integrated circuits, comprises a signal processing circuit 200, an RF (radio frequency) amplifier 220, a drive circuit 230, a microcomputer 240 and a DRAM (dynamic random access memory) 250.
The signal processing circuit 200 includes a DSP (digital signal processor) 201, a DAC (digital-to-analog converter) 202, a servo circuit 203 and an error correction circuit 204. The RF amplifier 220 is formed by a bipolar integrated circuit with different components, and the signal processing circuit 200 is integrated into a single chip by a CMOS (complementary metal oxide semiconductor) integrated circuit.
An optical pickup 210 converts data recorded on a CD-ROM disk to an RF signal, and outputs the RF signal to the RF amplifier 220. The RF amplifier 220 generates a reproduced signal (EFM (eight to fourteen modulation) signal), a focus error signal and a tracking error signal etc., and outputs these signals to the signal processing circuit 200.
The signal processing circuit 200 creates a control signal for controlling the optical pickup 210 from the focus error signal, the tracking error signal etc. through the DSP 201 and the servo circuit 203, and outputs the control signal to the drive circuit 230. The drive circuit 230 drives an actuator provided in the optical pickup 210 in response to the input control signal, for controlling the optical pickup 210 to reproduce an excellent RF signal.
The signal processing circuit 200 further performs error correction of the reproduced data by the error correction circuit 204 with the DRAM 250, for converting the reproduced data to an analog signal by the DAC 202 and outputting the analog signal when reproducing a sound signal.
The microcomputer 240 serves as a system controller control ling operations of the overall drive and transmits/receives data etc. to/from the signal processing circuit 200 at need so that the CD-ROM drive executes various operations.
The RF amplifier 220 of the CD-ROM drive having the aforementioned structure internally varies the amplification factor for the RF signal with various levels of RF signals for reproducing data from various optical disks such as a CD, a CD-ROM, a CD-RW (compact disk rewritable) and the like. Therefore, the RF amplifier 220 comprises a PGA (programmable gain amplifier) or the like varying the amplification factor for the RF signal, and employs a variable resistance circuit settable to various resistance values for gain control.
FIG. 15 is a circuit diagram showing the structure of a conventional variable resistance circuit. The variable resistance circuit shown in FIG. 15 includes a decoding circuit 300, switches SW0 to SW255 and resistors TR0 to TR255.
The 256 resistors TR0 to TR255 are serially connected with each other, the resistance values of all resistors TR0 to TR255 are set to R (xcexa9), and the resistors TR0 to TR255 are identical to each other. The switches SW0 to SW255, connected in parallel with the corresponding ones of the resistors TR0 to TR255 respectively, are identical to each other. When the switches SW0 to SW255 are turned on, the resistors TR0 to TR255 connected therewith are so bypassed as to change the resistance value of the variable resistance circuit.
Control signals d1 to d8 of eight bits are input in the decoding circuit 300. The control signal d1 expresses the least significant bit, the control signal d8 expresses the most significant bit, and the respective values of 0 to 255 can be expressed by the control signals d1 to d8. The decoding circuit 300 decodes the control signals d1 to d8 of eight bits and outputs control signals for turning on/off the switches SW0 to SW255 and setting resistance values corresponding to data expressed by the control signals d1 to d8 of eight bits to the switches SW0 to SW255.
The switches SW0 to SW255 are turned on/off by the control signals output from the decoding circuit 300 respectively, and the ON-state switches bypass the resistors. Therefore, the resistance value of the variable resistance circuit is set to an arbitrary value among 0 (xcexa9), R (xcexa9), 2R (xcexa9), . . . , 255R (xcexa9) by bypassing an arbitrary resistor among the 256 resistors TR0 to TR255 in response to the control signals d1 to d8 of eight bits.
FIG. 16 i s a circuit diagram showing the structure of another conventional variable resistance circuit. The variable resistance circuit shown in FIG. 16 includes switches SW10 to SW17 and resistors TR10 to TR17. The eight resistors TR10 to TR17 are serially connected with each other. The resistors TR10, TR11 and TR12 have resistance values R (xcexa9), 2R (xcexa9) and 4R (xcexa9) respectively, and the resistance value s of the subsequent resistors TR13 to TR17 are successively doubled so that the resistance value of the final resistor TR17 is set to 128 R (xcexa9).
The switches SW10 to SW17 are connected in parallel with the corresponding ones of the resistors TR10 to TR17 respectively, and turned on/off thereby bypassing the resistors TR10 to TR17 connected therewith.
The aforementioned control signals d1 to d8 of eight bits are input in the switches SW10 to SW17 respectively, for setting the resistance value of the variable resistance circuit to an arbitrary value among 0 (xcexa9), 2R (xcexa9), 255R (xcexa9).
As hereinabove described, the variable resistance circuit shown in FIG. 15 requires the 256 resistors TR0 to TR255 and the 256 switches SW0 to SW255 as well as the decoding circuit 300 decoding the control signals d1 to d8 of eight bits, in order to implement resolution of eight bits. Therefore, the circuit area of the variable resistance circuit is remarkably increased. When such a variable resistance circuit having a large circuit area is integrated with other circuits, the area of the integrated circuit is disadvantageously increased.
Further, linearity of the resistance value of the variable resistance circuit shown in FIG. 16 is deteriorated due to parasitic resistances of the switches SW10 to SW17. Assuming that the parasitic resistance value of each of the switches SW10 to SW17 is r (xcexa9), the resistance value of the variable resistance circuit is 255R (xcexa9) when all switches SW0 to SW17 are off, 254R+rxc3x97R/(r+R) (xcexa9) when the switch SW10 is on and the switches SW11 to SW17 are off, 253R+2rxc3x97R/(r+2R) (xcexa9) when the switch SW11 is on and the switches SW10 and SW12 to SW17 are off, or 252R+rxc3x97R/(r+R)+2rxc3x97R/(r+2R) (xcexa9) when the switches SW10 and SW11 are on and the switches SW12 to SW17 are off.
Thus, the change rate of the resistance value of the variable resistance circuit is Rxe2x88x92rxc3x97R/(r+R) (xcexa9), R+rxc3x97R/(r+R)xe2x88x922rxc3x97R/(r+2R) (xcexa9) or Rxe2x88x92rxc3x97R/(r+R) (xcexa9). In other words, even if the change rate of the resistance value by the resistors TR10 to TR17 is constant, the change rate of the resistance value by the parasitic resistances of the switches SW10 to SW17 is not constant. Therefore, the change rate is not constant but the linearity of the resistance value of the variable resistance circuit is deteriorated due to the parasitic resistances of the switches SW10 to SW17.
In order to ensure the linearity of the resistance value of the variable resistance circuit, the switches SW10 to SW17 must be sufficiently increased in size so that the parasitic resistances thereof hardly influence the resistance value of the variable resistance circuit. Thus, the circuit area of the variable resistance circuit is disadvantageously increased. When such a variable resistance circuit having a large circuit area is integrated with other circuits, the area of the integrated circuit is increased.
As hereinabove described, it is difficult to reduce the area of the conventional variable resistance circuit or to improve the precision of the resistance value although the area can be reduced. Thus, area reduction and improvement in precision cannot be compatibly attained in the conventional variable resistance circuit.
FIG. 17 shows a conventional time constant switching circuit used as a filter for example. Referring to FIG. 17, eight capacitors are switched for varying a time constant. First and second terminals of a resistor 1 form input and output terminals 2 and 3 respectively. A plurality of switches 4a to 4h are connected in parallel with the output terminal 3, and grounded capacitors 5a to 5h having different capacitance values are connected to second terminals of the switches 4a to 4h respectively with relation of C(5a) less than C(5c) . . .  less than C(5h) between the capacitance values. Control signals 6a to 6h on-off control the switches 4a to 4h respectively.
In the circuit shown in FIG. 17, the time constant is decided by the product of the resistance value of the resistor 1 and the sum of the capacitance values connected to the output terminal 3. Thus, it is possible to change the capacitance values connected to the output terminal 3 and vary the time constant by controlling the switches 4a to 4h. 
When selecting the capacitor 5a having the minimum capacitance value, for example, only the control signal 6a turns on only the switch 4a as an xe2x80x9cONxe2x80x9d level. At this time, the control signals 6b to 6h for the remaining switches 4b to 4h are brought into OFF states. Therefore, only the capacitor 5a is connected to the output terminal 3 for implementing the time constant decided by the product of the resistance value of the resistor 1 and the capacitance value of the capacitor 5a. When connecting a plurality of capacitors such as the capacitors 5a and 5b, for example, the switches 4a and 4b are turned on and the remaining switches 4c to 4h are turned off.
In the aforementioned structure, however, the time constant is influenced by parasitic capacitances of the switches 4a to 4h. FIG. 18 shows a switch formed by an N-channel transistor 7. Referring to FIG. 18, source and drain terminals of the N-channel transistor 7 form input and output terminals 8 and 9 of the switch respectively. Further, a gate terminal of the transistor 7 forms a control terminal 10 of the switch. When forming the switch by the N-channel transistor 7 in the aforementioned manner, diffusion capacitances 11 and 12 are present on the input and output terminals 8 and 9 of the switch as parasitic capacitances respectively. When the switch is on, further, gate capacitances 13 and 14 are present as parasitic capacitances in addition to the aforementioned diffusion capacitances 11 and 12.
Therefore, when connecting only the capacitor 5a in FIG. 17, for example, parasitic capacitances (diffusion capacitances) of the OFF-state switches 4b and 4h are also added to the output terminal 3 in addition to the parasitic capacitance of the ON-state switch 4a, and hence the time constant is disadvantageously increased to deteriorate a filter characteristic. There is a tendency that such influence is remarkable particularly when using a small capacitor, i.e., when the time constant is small.
An object of the present invention is to provide a variable resistance circuit capable of reducing the circuit area and setting the resistance value in high precision, an operational amplification circuit employing this variable resistance circuit and a semiconductor integrated circuit employing this operational amplification circuit.
Another object of the present invention is to provide an operational amplification circuit capable of reducing the circuit area and having an excellent frequency characteristic and a semiconductor integrated circuit employing this operational amplification circuit.
Still another object of the present invention is to provide a filter time constant switching circuit suppressing deterioration of a filter characteristic resulting from a parasitic capacitance in a switch part for varying a capacitance value deciding the time constant of a filter.
A variable resistance circuit according to an aspect of the present invention comprises serially connected N (N: integer of at least 2) resistors and N switches connected in parallel with the N resistors respectively and selectively turned on or off, while the resistance value of at least one of the resistors is different from the resistance value of another resistor and the resistance value of a parasitic resistance of each of the N switches in an ON state is in proportion to or in positive correlation similar to proportion to the resistance value of the resistor connected in parallel with this switch.
In the variable resistance circuit, the N resistors are serially connected with each other, and the switches are connected in parallel with the N resistors respectively and turned on so that the resistors connected with the ON-state switches are bypassed to change the resistance value. At least one of the N resistors has a different resistance value, and hence various resistance values can be set in excess of the number of the resistors by varying combination of the bypassed resistors and a number of resistance values can be set with a small circuit area. Further, the parasitic resistance value of the ON-state switch is in proportion to or in positive correlation similar to proportion to the resistance value of the resistor connected in parallel with this switch, whereby the combined resistance value of the parasitic resistance of the switch and the resistor is in proportion to the resistance value of the resistor and linearity of the resistance value of the variable resistance circuit can be ensured. Consequently, the circuit area of the variable resistance circuit can be reduced while the resistance value can be set in high precision.
Each of the N switches may include a transistor connected in parallel with each resistor, and the resistance value of the resister may be in inverse proportion to or in negative correlation similar to inverse proportion to the gate width of the transistor connected in parallel with this resister.
In this case, the resistance value of the resister is in inverse proportion to or in negative correlation similar to inverse proportion to the gate width of the transistor so that the resistance value of a parasitic resistance of the transistor can be in proportion to the resistance value of the resistor, whereby the parasitic resistance can be controlled by simply changing the gate width and the variable resistance circuit can be readily manufactured.
Each resistance value of the N resistors may be set to Rxc3x972i (xcexa9) (i: integer of 0 to (Nxe2x88x921)), and the resistance value of each parasitic resistance of the N switches may be set to rxc3x972i (xcexa9) .
In this case, 2N resistance values can be set with the N resistors, whereby the circuit area of the variable resistance circuit can be extremely reduced while the resistance value can be set to an arbitrary level among the 2n resistance values by control signals of N bits so that the variable resistance circuit can be readily controlled.
The switches may be formed by CMOS switches. In this case, a circuit including the variable resistance circuit can be formed by a CMOS integrated circuit.
An operational amplification circuit according to another aspect of the present invention comprises a variable resistance circuit and an operational amplifier, connected with the variable resistance circuit, having an amplification factor varying with the resistance value of the variable resistance circuit, while the variable resistance circuit includes serially connected N (N: integer of at least 2) resistors and N switches connected in parallel with the N resistors respectively and selectively turned on or off, the resistance value of at least one of the resistors is different from the resistance value of another resistor, and the resistance value of a parasitic resistance of each of the N switches in an ON state is in proportion to or in positive correlation similar to proportion to the resistance value of the resistor connected in parallel with this switch.
In the operational amplification circuit, the aforementioned variable resistance circuit is connected with the operational amplifier for varying the amplification factor with the resistance value of the variable resistance circuit capable of varying the resistance value in high precision, whereby the amplification factor can be set in high precision while the circuit area of the operational amplification circuit can be reduced due to the small circuit area of the variable resistance circuit.
The variable resistance circuit may be connected to an input terminal of the operational amplifier, and the resistor having the maximum resistance value may be connected to the input terminal among the N resistors.
In this case, the switches form parasitic capacitances on nodes connecting the resistors and the variable resistance circuit is influenced by a CR time constant by the parasitic capacitances and the resistors, while the resistor connected to the input terminal has the maximum resistance value and hence the parasitic capacitance acting on the resistor having the maximum resistance value is so minimized that the CR time constant of the variable resistance circuit itself can be totally reduced and an operational amplification circuit having an excellent frequency characteristic can be implemented.
A semiconductor integrated circuit according to still another aspect of the present invention, receiving an output signal from an optical pickup, comprises an operational amplification circuit amplifying the output signal from the optical pickup and another circuit, while the operational amplification circuit and the other circuit are integrated into a single chip by a CMOS integrated circuit, the operational amplification circuit includes a variable resistance circuit and an operational amplifier, connected with the variable resistance circuit, having an amplification factor varying with the resistance value of the variable resistance circuit, the variable resistance circuit includes serially connected N (N: integer of at least 2) resistors and N switches connected in parallel with the N resistors respectively and selectively turned on or off, the resistance value of at least one of the resistors is different from the resistance value of another resistor, and the resistance value of a parasitic resistance of each of the N switches in an ON state is in proportion to or in positive correlation similar to proportion to the resistance value of the resistor connected in parallel with this switch.
The semiconductor integrated circuit employs the aforementioned operational amplification circuit capable of setting the amplification factor in high precision and reducing the circuit area for the amplification circuit amplifying the output signal from the optical pickup and integrates the amplification circuit and the other circuit into a single chip by the CMOS integrated circuit, whereby a one-chip CMOS integrated circuit for an optical disk drive including a high-precision amplification circuit having a reduced area can be implemented.
An operational amplification circuit according to a further aspect of the present invention comprises an operational amplifier and a variable resistance circuit connected to an input terminal of the operational amplifier, while the variable resistance circuit includes serially connected N (N: integer of at least 2) resistors and N switches connected in parallel with the N resistors respectively and selectively turned on or off, the resistance value of at least one of the resistors is different from the resistance value of another resistor, and the resistor having the maximum resistance value is connected to the input terminal among the N resistors.
The N resistors are serially connected with each other, and the switches are connected in parallel with the N resistors respectively and turned on so that the resistors connected with the ON-state switches are bypassed to change the resistance value. At least one of the N resistors has a different resistance value, and hence various resistance values can be set in excess of the number of the resistors by varying combination of the bypassed resistors and a number of resistance values can be set with a small circuit area.
The switches form parasitic capacitances on nodes connecting the resistors and the variable resistance circuit is influenced by a CR time constant by the parasitic capacitances and the resistors, while the resistor connected to the input terminal has the maximum resistance value and hence the parasitic capacitance acting on the resistor having the maximum resistance value is so minimized that the CR time constant of the variable resistance circuit itself can be totally reduced and an operational amplification circuit having an excellent frequency characteristic can be implemented.
In this case, the N resistors are preferably arranged in order of the resistance values. Thus, the influence by the CR time constant resulting from the parasitic capacitances of the switches and the resistors can be reduced for preventing deterioration of the frequency characteristic.
Each resistance value of the N resistors is preferably set to Rxc3x972i (xcexa9) (i: integer of 0 to (Nxe2x88x921)).
Thus, 2N resistance values can beset with the N resistors, whereby the circuit area of the variable resistance circuit can be extremely reduced while the resistance value can be set to an arbitrary level among the 2N resistance values by control signals of N bits so that the variable resistance circuit can be readily controlled.
The variable resistance circuit preferably includes a fixed resistor arranged between the resistor having the maximum resistance value and the input terminal.
The switches are preferably formed by CMOS switches.
The variable resistance circuit is preferably used as a resistance circuit forming a feedback loop of the operational amplifier, and the amplification factor of the operational amplifier preferably varies with the resistance value of the variable resistance circuit.
Thus, the amplification factor is varied with the resistance value of the variable resistance circuit having an excellent frequency characteristic, whereby the amplification factor can be set in high precision while the circuit area of the operational amplification circuit can be reduced due to the small circuit area of the variable resistance circuit.
The operational amplification circuit may further comprise a resistance circuit, forming a feedback loop of the operational amplifier, including a fixed resistor, an input signal may be input in the operational amplifier through the variable resistance circuit, and the operational amplifier, the variable resistance circuit and the resistance circuit may constitute a programmable gain amplifier.
Thus, the switches exert no bad influence on the characteristics in the feedback loop, and a boost can be suppressed at a high frequency.
A semiconductor integrated circuit according to a further aspect of the present invention, receiving an output signal from an optical pickup, comprises an operational amplification circuit amplifying the output signal from the optical pickup and another circuit, while the operational amplification circuit and the other circuit are integrated into a single chip by a CMOS integrated circuit, the operational amplification circuit includes an operational amplifier and a variable resistance circuit connected to an input terminal of the operational amplifier, the variable resistance circuit includes serially connected N (N: integer of at least 2) resistors and N switches connected in parallel with the N resistors respectively and selectively turned on or off, the resistance value of at least one of the resistors is different from the resistance value of another resistor, and the resistor having the maximum resistance value is arranged on the side of the input terminal among the N resistors.
Thus, the frequency characteristic of the amplification circuit amplifying the output signal from the optical pickup is improved and the circuit area can be reduced, while a one-chip CMOS integrated circuit for an optical disk drive including the amplification circuit having an excellent frequency characteristic and a reduced area can be implemented.
A time constant switching circuit according to a further aspect of the present invention comprises a resistor having a first terminal forming an input terminal and a second terminal forming an output terminal, a plurality of time constant switching capacitors for varying a capacitance value connected to the output terminal, a first switch controlled by a time constant control signal for changing the capacitance value connected to the output terminal and a second switch, while the plurality of time constant switching capacitors are divided into a plurality of groups, a group including the capacitor having the minimum capacitance value is directly connected to the output terminal, and another group is connected to the output terminal through the second switch.
Thus, when implementing a smaller time constant, the number of switches connected to the output terminal can be reduced and the parasitic capacitances of the switches can be reduced for suppressing characteristic deterioration resulting from the parasitic capacitances.
The group including the capacitor having the minimum capacitance value may be formed by a single capacitor. Thus, only a single OFF-state switch is connected to the output terminal when implementing the minimum time constant, whereby characteristic deterioration caused by a parasitic capacitance can be suppressed.
The plurality of groups of the capacitors may be connected successively from the group including the capacitor having the minimum capacitance value. Thus, the parasitic capacitances of the switches can be reduced as the implemented time constant is reduced, whereby characteristic deterioration caused by a parasitic capacitance can be suppressed.
A waveform shaping circuit according to a further aspect of the present invention comprises a resistor having a first terminal receiving an input and a second terminal, a differential amplifier having an inversion input terminal connected to the second terminal of the resistor, resistors serially connected between the inversion input terminal and an output terminal of the differential amplifier and a time constant switching circuit connected to a node of the resistors serially connected, while the time constant switching circuit includes a resistor having a first terminal forming an input terminal and a second terminal forming an output terminal, a plurality of time constant switching capacitors for varying a capacitance value connected to the output terminal, a first switch controlled by a time constant control signal for changing the capacitance value connected to the output terminal and a second switch, the plurality of time constant switching capacitors are divided into a plurality of groups, a group including the capacitor having the minimum capacitance value is directly connected to the output terminal, and another group is connected to the output terminal through the second switch. Thus, a waveform shaping circuit having small characteristic deterioration caused by a parasitic capacitance can be implemented.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.